Tag Archives: 28nm

28nm-SLP technology – The Superior Low Power, GHz Class Mobile Solution

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By Kelvin Low

In my previous blog post, I highlighted our collaborative engagement with Adapteva as a key factor in helping them deliver their new 64-core Epiphany-4 microprocessor chip. Today I want to talk about the second key ingredient in enabling their success: the unique features of our 28nm-SLP technology.

As the Product Marketing lead for our leading edge technologies, I am always intrigued by some of the discussion threads in the industry, especially during the introduction of the 28nm roadmap. We have done extensive study, gathering inputs from our customers, the design community, market segment experts and end product companies. The various inputs of requirements that the industry wanted of a 28nm technology node can be summarized in a few bullet points:

  • At least 35% performance scaling from prior low power node.
  • Leakage and power reduction of at least 40% from prior node.
  • 50% area scaling or 2x more device density, a critical need for increased feature integration on the SoC.
  • And of course fastest time to design and time to market.

We came up with the perfect solution – 28nm-SLP. The result of our collaboration with our partners in the Joint Development Alliance (JDA), the technology is implemented using our unique high-k metal gate (HKMG) Gate First integration. Why?

1.  HKMG

Gate oxide thickness scaling was reaching its limits at the 40nm node. We had seen significant product leakage issues and there had to be design workarounds to bring the leakages down to acceptable levels, but this results in inefficient designs leading to product area increase.   As we scale down to 28nm, there’s a need to maintain good short channel control and to do this, we have to push the electrical gate dielectric thinner.  This is tricky.  Studies have shown that if we thin down the gate dielectric material used in 40nm, which is Poly-Silicon OxyNitride (PolySiON), gate leakage will increase to unacceptable levels.  So, high-k dielectric was introduced.   Metal gate was included as part of the overall integration to achieve the right work function for the transistors.  The result – product performance improvements of more than 35% and 40% lower power than 40nm.

2.  Gate First Integration

HKMG can be realized with two main approaches: Gate First or Gate Last implementation.  While it is well known that Intel employed the Gate Last HKMG approached for their 45nm CPU technology, GLOBALFOUNDRIES concluded that this was not the most optimum approach for our customers. We (and our JDA partners) chose the Gate First integration at 32/28nm as it provided clear benefits in the following areas:

  • Simpler process integration, which results in a less complex and cost effective technology.
  • No need for complex (and expensive) stress engineering for our 28nm-SLP (e.g. no embedded SiGe source/drain modules) in contrast to something like a ‘low power’ PolySiON or high performance HKMG alternatives.
  • None of the design restrictions associated with a Gate Last implementation.  We allow dual gate orientation, poly jogs and have simpler analog related design rules.  Through various designers’ feedback, it was conclusive that our technology results in a 10-15% smaller die size, easy analog implementation and easier to port key complex IPs from the prior node (vs. a PolySiON or Gate Last HKMG alternatives)

The net result: our technology provides a 100% increase in gate density and easier implementation of IPs allows for faster (and lower risk) design turn around.

There are many more benefits that I could share, but the most important proof point of our technology is where we are today in terms of volume production. Silencing the skeptics that HKMG Gate First was not a manufacturable technology, we have already shipped more than 350,000 wafers of HKMG today – the largest number of wafers among all pure play foundries. End products are already available on the shelf and have shown superior performance from benchmarking data.

In the relentless drive to move into the next leading edge node, GLOBALFOUNDRIES has been working with our lead partners at the next nodes (20nm and 14nm) for more than 18 months. New technology elements and innovations like double patterning, middle of line (MOL) modules, and FinFET transistors are complex elements that will be required allow Moore’s law scaling to continue. Again, we are collaborating with our customers and design ecosystem partners to devise the best solution for the industry. Only by early and close partnerships will we have win-win solutions with our customers and partners.

Kelvin Low is Product Marketing Deputy Director for GLOBALFOUNDRIES, responsible to define GLOBALFOUNDRIES leading edge technology roadmaps and product solutions. He is also an active member of the Joint Development Alliance where he is the marketing lead providing key market inputs in shaping the next technology nodes.